The present invention relates to a high-speed, multi-functional semiconductor logic circuit device.
As such semiconductor logic circuit devices, various types of devices have been proposed. As a conventional logic circuit expected to perform a high-speed operation, a circuit as in FIG. 18 has been proposed. A similar arrangement is disclosed by McCarthy, "Mos Devices and Circuit Design", John Willey & Sons. The logic circuit shown in FIG. 18 is an inverter constituted by a combination of enhancement and depletion type MOSFETs. In this case, an enhancement type element 50 is used as a driver element, whereas a depletion type element 51 is used as a load element. Assume first that a pulse input is supplied to the input terminal of the driver element 50, and the input level changes from low level to high level. In this case, the driver element 50 is switched from an OFF state to an ON state, and the output voltage changes from high level to low level. With this change in level, the charge accumulated in an output capacitor 52 is extracted by a current flowing in the driver element 50. Therefore, a switching time .tau..sub.on is given by EQU .tau..sub.on =C.sub.out .multidot.VL/(gm.sup.d .multidot.VL)=C.sub.out /gm.sup.d
where C.sub.out is the output capacitance, VL is the change in output voltage, and gm.sup.d is the average transconductance of the driver element.
Assume next that the input level of the driver element 50 changes from high level to low level. Similar to the above case, EQU .tau..sub.off =C.sub.out .multidot.VL/(gm.sup.1 .multidot.VL)=C.sub.out /gm.sup.1
where gm.sup.1 is the average transconductance of the load element 51.
As indicated by the above equations, the switching speed at which low level is switched to high level, or vice versa is equal to the value obtained by dividing the output capacitance C.sub.out by the average transconductance gm.sup.d or gm.sup.1. If the fan-out and the input capacitance of an element are respectively represented by m and C.sub.in, and the wiring capacitance is neglected, the output capacitance is given by EQU C.sub.out =mC.sub.in
Therefore, the switching time of the inverter having such an arrangement is increased in proportion to the fan-out. That is, the operating speed of a conventional logic gate is decreased with an increase in fan-out. The arrangement constituted by MOSFETs has been described above, because the input capacitor and the driving performance for charging it are closely related to each other. The above-described problem equally applies to other circuit arrangements (e.g., a circuit constituted by CMOSs).